The autoCircuits SPICE service allows Users to specify a circuit and the desired type of analysis through a SPICE-like netlist. Differently from the standard autoCircuits generation process, which is based on a randomized graph and element selection, the autoCircuits SPICE service is intended to supply a precise and well-defined circuit to the web solution engine. SPICE is only used as a standardized language for specifying the netlist: no call to any SPICE solver is performed, since all analyses are carried out through the internal autoCircuit solvers.
A number of restrictions apply. In particular, only element types can be specified but not their numeric value. The autoCircuits service is not intended as a web-based cheating solution for exams, but rather a support for Students in preparing exams... The numeric value of all elements will thus be randomized, according to the main philosophy of this service. This is why the netlist to be provided is not fully SPICE-compatible (see below for details).
Once the netlist is ready, clicking on the circuit generation button will submit the netlist to the autoCircuits SPICE service engine, which will analyze the circuit for errors. In case of no errors, the circuit will be drawn in a PDF file, together with the problem statement as decoded from the requested SPICE analysis, and the corresponding solution. The PDF will then be made available for download.
A User-defined circuit topology can be provided by typing or copying-pasting the corresponding SPICE netlist in the dedicated text box. Only up to 15 lines are currently allowed. An automated syntax-checking engine will verify the netlist on the fly and will display the validated netlist (green color) in the dedicated text box, including informative error messages (gray insets) that will help the User to correct any mistakes. Only when the netlist is validated (no error messages, text displayed in green) the circuit can be submitted.
Some general syntax rules apply:
In the following, characters to be typed exactly as in this guide are denoted like this, whereas characters or strings that must be replaced with user-defined choices are typeset like this.
Any circuit element is specified through a dedicated netlist line. For each two-terminal element, the positive and negative nodes to which the element is connected must follow the element name (separated by a space). All two-terminal elements obey the normal sign reference for voltage and current. For multi-terminal elements, the node sequence must include all the element interface nodes. In the following,
For some elements, additional modifiers are required to better specify the element type. In some cases, these modifiers are SPICE standard, but not for all elements. Compliance to the SPICE standard is specified for each listed element below.
Any characters that follow the required element specification will be discarded in the validated netlist. This allows to type in a SPICE standard netlist, including element values. These values are treated as extra characters and will be discarded.
R_name node+ node-
If provided, the element value will be discarded and replaced by a new randomized value.
C_name node+ node-
If provided, the element value will be discarded and replaced by a new randomized value.
L_name node+ node-
If provided, the element value will be discarded and replaced by a new randomized value.
K_name L_name1 L_name2
where L_name1, L_name2 are the element names of the two coupled inductors (must be present in the netlist). If provided, the coupling coefficient will be discarded and replaced by a new randomized value. Note: only one coupling element is currently supported.
V_name node+ node- sourcetype
I_name node+ node- sourcetype
The modifier sourcetype defines the source type and can be one of the following choices:
S_name node+ node- switchtype
The modifier switchtype defines the switch type and can be one of the following choices:
E_name node+ node- ctrlnode+ ctrlnode-
G_name node+ node- ctrlnode+ ctrlnode-
The sources are controlled by the voltage between nodes ctrlnode+, ctrlnode-. If provided, voltage gain or transconductance will be discarded and replaced by a new randomized value.
H_name node+ node- element
F_name node+ node- element
The sources are controlled by the current through element, which must be present in the netlist. If provided, transresistance or current gain will be discarded and replaced by a new randomized value.
P_name node+ node-
Defines an interface port to be used for computing equivalent resistances/impedances, Thevenin/Norton equivalents, and two-port matrices, see below.
O_name node+ node- nodeout
Defines an ideal (infinte-gain) Operational Amplifier with non-inverting, inverting, and output terminals node+, node-, nodeout. The autoCircuits engine will replace the component with two elements: one nullator between nodes (node+,node-) and one norator between nodes (nodeout,0).
X_name node1+ node1- node2+ node2- TRAFO
Defines an ideal transformer with its primary port connected to node1+, node1- and its secondary port connected to node2+, node2-.
Analysis types are defined by a single control line beginning with a dot. This is similar to the SPICE standard, but the available analysis types extend and/or modify what is provided by the usual SPICE syntax, due to the different nature and scope of the autoCircuits simulator.
Most analysis types follow the same general syntax
analysistype modifier outputs
where
Here follows the list of allowed analysis types with some examples. Note that each analysis imposes particular restrictions on the allowed circuit elements. These restrictions are checked by the server, and in case of violations the analysis will not be performed. All such restrictions are discussed below for each analysis type.
.DC Req P_name
Finds the equivalent resistance at port P_name, where P_name is the name of a valid port in the netlist. All independent sources will be switched off.
Restrictions: only resistive and time-invariant components are allowed in the netlist (no inductors, capacitors and switches); only sources of type DC or 0 are allowed; netlist must include a single port element.
.DC Solve V(node+,node-) I(element)
Solves the circuit under DC conditions for the voltage between nodes node+,node- and the current through element.
Restrictions: only resistive and time-invariant components are allowed in the netlist (no inductors, capacitors and switches); only sources of type DC or 0 are allowed, but there must be at least one source of type DC; netlist must not include port elements.
.DC Thevenin P_name
.DC Norton P_name
Finds the Thevenin/Norton equivalent circuit at port P_name, where P_name is the name of a valid port in the netlist.
Restrictions: only resistive and time-invariant components are allowed in the netlist (no inductors, capacitors and switches); only sources of type DC or 0 are allowed; netlist must include a single port element.
.DC MNA
Finds the Modified Nodal Analysis system of a resistive circuit.
Restrictions: only resistive and time-invariant components are allowed in the netlist (no inductors, capacitors and switches); only sources of type DC or 0 are allowed, but there must be at least one source of type DC; netlist must not include port elements.
.DC matrixtype P_name1 P_name2
Characterizes the resistive two-port element defined by ports with names P_name1 and P_name2 through the following matrices (replace matrixtype with):
Restrictions: only resistive and time-invariant components are allowed in the netlist (no inductors, capacitors and switches); only sources of type 0 (deactivated sources) are allowed; netlist must include exactly two port elements.
.AC Zeq P_name
Finds the AC equivalent impedance at port P_name, where P_name is the name of a valid port in the netlist. All independent sources will be switched off, and any other port will be left open. The operation frequency will be randomized.
Restrictions: no switches are allowed in the netlist; only sources of type AC or 0 are allowed; netlist must include a single port element.
.AC Solve V(node+,node-) I(element)
Solves the circuit under AC conditions for the voltage between nodes node+,node- and the current through element.
Restrictions: no switches are allowed in the netlist; only sources of type AC or 0 are allowed, but there must be at least one source of type AC; netlist must not include port elements.
.AC Thevenin P_name
.AC Norton P_name
Finds the Thevenin/Norton equivalent circuit at port P_name, where P_name is the name of a valid port in the netlist, under AC conditions (with randomized operation frequency) and randomized sources. All AC sources are constrained to the same operation frequency.
Restrictions: no switches are allowed in the netlist; only sources of type AC or 0 are allowed; netlist must include a single port element.
.AC Power element
Finds active and reactive power absorbed by element under AC conditions (with randomized operation frequency) and randomized sources. All AC sources are constrained to the same operation frequency.
Restrictions: no switches are allowed in the netlist; only sources of type AC or 0 are allowed, but there must be at least one source of type AC; netlist must not include port elements.
.AC Multifreq V(node+,node-) I(element)
Solves the circuit under steady-state conditions for the voltage between nodes node+,node- and the current through element. All sources are randomized, including individual operation frequency. DC sources are treated as randomized DC sources.
Restrictions: no switches are allowed in the netlist; only sources of type AC, DC or 0 are allowed, but there must be at least one source of type AC; netlist must not include port elements.
.TRAN Iorder V(node+,node-) I(element)
Solves the first-order circuit with DC sources using the asymptotic method. Circuit is checked for compliance with this analysis (only one dynamic element, only DC sources, switches, and resistive elements). Returns on output the voltage between nodes node+,node- and the current through element.
Restrictions: netlist must include exactly one dynamic element; only sources of type DC or 0 are allowed, but there must be at least one source of type DC; netlist must not include port elements.
Note: only first-order circuits with a finite time constant are properly handled. If this is not the case, the solver will detect the circuit as degenerate or ill-defined.
.TF source V(node+,node-) I(element)
Finds the transfer function between source source (which must exist in the netlist and which must be of type TF) and the listed outputs, in this case the voltage between nodes node+,node- and the current through element.
Restrictions: only sources of type TF are allowed, and at least one source must be present; netlist must not include port elements.
.IR source V(node+,node-) I(element)
Finds the impulse response due to source source (which must exist in the netlist and which must be of type TF) and the listed outputs, in this case the voltage between nodes node+,node- and the current through element.
Restrictions: only sources of type TF are allowed, and at least one source must be present; netlist must not include port elements.
.LTI Poles
Finds the natural frequencies (poles) of the network.
Restrictions: netlist must not include port elements and switches.
.LTI StateEq V(node+,node-) I(element)
Writes the State Equations of the circuit, including the ouptut equations for the listed variables, in this case the voltage between nodes node+,node- and the current through element. Only the regular (non-degenerate) case is currently supported.
Restrictions: netlist must not include port elements and switches; only sources of type DC or 0 are allowed, but there must be at least one source of type DC.
.TRAN Solve V(node+,node-) I(element)
Finds the general transient solution for the listed variables, in this case the voltage between nodes node+,node- and the current through element. Initial conditions on state variables are determined from the circuit based on the definition of the various sources.
Restrictions: netlist must include at least one dynamic element; only sources of type DC, DC_on, DC_off, AC, AC_on, AC_off, 0 are allowed, but there must be at least one non-vanishing source; netlist must not include port elements.
.LTI MNA
Finds the Modified Nodal Analysis system for a general LTI circuit.
Restrictions: netlist must not include port elements and switches; only sources of type DC or 0 are allowed, but there must be at least one source of type DC.
.LTI matrixtype P_name1 P_name2
Characterizes the LTI two-port element defined by ports with names P_name1 and P_name2 through the following Laplace-domain matrices (replace matrixtype with):
Restrictions: netlist must not include switches; only sources of type 0 (deactivated sources) are allowed; netlist must include exactly two port elements.